The present invention relates to a magnetic head read/write preamplifier within a magnetic storage system, and particularly to a write driver circuit within the read/write preamplifier having improved switching speed, improved rise/fall time, reduced write current ringing, and reduced asymmetry.
In magnetic data storage systems, a magnetic read/write head is operable to write binary data, representing ones and zeros, onto a magnetic medium such as a magnetic tape or disc. The head uses an inductive coil to generate magnetic fields, which form magnetic patterns on the medium representing the ones and zeros. The orientation of the patterns depends on the direction of electrical current flow through the inductive coil, so that writing the binary data entails selectively changing, or reversing, the direction of current flow through the head. Changing the direction of current flow through the coil is the function of a write driver.
The write driver includes a drive circuit, coupled to the head, and a control circuit for operating the drive circuit in response to control data signals. Conventionally, the drive circuit is configured as an H-switch, which has a pair of forward switches and a pair of reverse switches. (The term H-switch stems from the H-shaped arrangement of the four switches and the head in electrical schematics.) The control circuit is conventionally responsive to a pair of complementary, or differential, control data signals to selectively open and close the forward and reverse switches of the H-switch, thereby changing the direction of current through the head to write a specific bit pattern on the magnetic medium.
The major components of the write driver are usually formed from transistors, which serve as switches. For example, FIG. 1 shows a typical write driver 10 coupled to a head 11 that includes an inductive coil L.sub.H. Write driver 10 includes an H-switch drive circuit 12 and a differential control circuit 14. The H-switch drive circuit, connected between opposite supply terminals such as V.sub.CC and ground, includes four drive transistors Q1-Q4, two head terminals 16 and 18, and a write current source I.sub.W. Transistors Q1 and Q4 serve as forward switches, and transistors Q2 and Q3 serve as reverse switches.
Differential control circuit 14 comprises control transistors Q5 and Q6, pull-up resistors R1 and R2, and pre-driver control current source I.sub.D, and operates the forward and reverse switches Q1-Q4 in response to write control signals at write control inputs V.sub.X and V.sub.Y. Specifically, when input V.sub.Y is a higher voltage than input V.sub.X, control circuit 14 closes, or turns on, control transistor switch Q5, and opens, or turns off, control transistor switch Q6. This arrangement turns on the forward switches Q2 and Q3 and turns off the reverse switches Q1 and Q4. As a result, current I.sub.W flows from V.sub.CC through switch Q2, head 11 from terminal 18 to terminal 16, and switch Q3 into the ground of the circuit. Conversely, when input V.sub.X is at a higher voltage than input V.sub.Y, control circuit 14 turns on control transistor switch Q5 and turns off control transistor switch Q6, thereby turning on the reverse switches and turning off the forward switches. This directs write current I.sub.W through switch Q1, head 11 from terminal 16 to terminal 18, and switch Q4 into the ground of the circuit. Thus, changing the relative voltage levels at inputs V.sub.X and V.sub.Y changes the direction of write current flow through head 11.
In practice, the write driver of FIG. 1 suffers from two problems. First, its constituent transistors have inherent switching speed limitations which inhibit the write driver and head from writing data as quickly and as densely as is necessary in high performance data storage systems. Second, the current flowing through the head immediately following a change in the direction of current flow tends to "overshoot" the desired value of write current, resulting in an additional delay for the write current to settle at its desired value after a transition.
The transistors forming the write driver suffer from switching limitations. Unlike ideal switches, transistors have inherent structural, or parasitic, capacitances which prevent them from instantaneously opening (turning off) or closing (turning on). These capacitances charge or discharge while opening or closing the transistor switch, and thus slow or delay the opening and closing of the transistor switch. The delays in opening and closing not only limit how fast bits are written but ultimately how closely the bits are spaced on a magnetic medium. The closeness of the bits, which is known as bit density, is a factor in the data capacity of a magnetic medium.
One particular aspect of this switching limitation or problem concerns transistors Q1-Q4, the four drive transistors of the H-switch drive circuit. These transistors have a larger surface area than control circuit transistors Q5 and Q6, enabling them to conduct the relatively large write current necessary for operating the write head. Larger transistors generally have larger inherent capacitances, which require more time to charge and discharge than do smaller capacitances. Thus, within the write driver, the four H-switch drive transistors Q1-Q4 are a significant factor limiting switching speed and bit density.
To alleviate the switching limitations of the H-switch drive transistors, artisans have sought to increase the capacity of control circuit 14 to rapidly charge and discharge the larger inherent capacitances of these transistors and thereby reduce their turn-on and turn-off times. There are several known approaches for increasing the current charging the drive transistors and thereby reducing their turn-on times.
One approach entails increasing current flow through resistors R1 and R2, known as pull-up resistors. Unfortunately, increasing the current flow through resistors R1 and R2 also reduces the voltage across the write head, known as head swing, which in turn reduces switching speed. Head swing determines the rate of change of current in the write head, which in turn determines how fast current in the write head itself can actually start, stop, and reverse direction in writing individual data bits. Reducing head swing therefore reduces switching speed. This approach is especially inadequate in low-voltage applications where any reduction in head swing significantly reduces switching speed.
A second approach entails connecting separate NPN emitter-follower circuits between the respective pull-up resistors R1 and R2 and the respective bases, or control nodes, of drive transistors Q1 and Q2. More particularly, an NPN emitter-follower includes an NPN transistor with its base connected to pull-up resistor R1, its collector coupled to the positive voltage supply terminal V.sub.CC, and its emitter coupled to the base of transistor Q1 and to the ground terminal through a pull-down resistor. When activated, the NPN transistor drives an emitter current into the base of upper drive transistor Q1 that rapidly charges the capacitance of transistor Q1 and thus accelerates its turn-on. When deactivated, the NPN transistor allows the capacitance of upper drive transistor Q1 to passively discharge through the pull-down resistor to the ground terminal. The counterpart emitter-follower between resistor R2 and the control node of upper drive transistor Q2 operates similarly. Unlike the first approach of increasing current flow in the pull-up resistors, the NPN emitter-follower circuits improve the turn-on times of the upper drive transistors without diminishing headswing. However, this approach is also inadequate because it improves only the turn-on times, and not the turn-off times of the upper drive transistors.
A third approach entails connecting separate PNP pull-down transistor circuits between the respective control nodes of transistors Q3 and Q4 and the ground terminal of the circuit. A write driver incorporating this technique is described in U.S. Pat. No. 5,532,631 (Ngo et al.), which is hereby incorporated by reference herein. This technique alternately supplies base current to the switching drive transistors to charge their parasitic capacitances and sinks base current from the switching drive transistors to discharge their parasitic capacitances.
A technique for improving both the turn-on and the turn-off times of the drive switching transistors entails charging and discharging their capacitances using respective MOSFET (metal-oxide-semiconductor field effect transistor) inverters. A write driver incorporating this technique is shown in U.S. Pat. No. 5,296,975 (Contreras). Contreras, however, uses both bipolar junction transistors and MOSFETs which makes it more complicated to manufacture than a pure bipolar or MOS design. Thus, even though the Contreras write driver includes MOS inverters for charging and discharging the capacitances of its upper drive transistors, its complexity and manufacture are significant drawbacks.
In addition to the inherent switching limitation of the drive transistors, the write driver of FIG. 1 also suffers from the second problem of the write current "overshooting" the desired value immediately following a change in current flow direction through the head. Specifically, during the starting and stopping and reversing of write current direction, the inductive coil in the write head inevitably exhibits a phenomenon, known as self-inductance, which produces a transient voltage, that is, a voltage spike, across the write head. The voltage spike, commonly called kickback, typically produces a ringing, or oscillating, voltage that lasts several nanoseconds before decaying to a negligible magnitude. These voltage spikes cause excessive write current to flow through the head following a reversal in the direction of current flow, to overcome the inductive coil's resistance to the current direction change. As a result, the write current exceeds its desired value and an additional delay time, known as settling time, is required for the oscillating write current to settle to the desired value. The additional delay slows total transition time and thereby inhibits the density of bit recording on the magnetic medium, which is desirably as high as possible.
One known solution to the ringing problem has been to connect a damping resistor across the terminals of the write head. The resistive damping reduces the settling time for the write current flowing through the head. However, resistive damping has several negative effects on the performance of the write circuit. Since some of the write current is diverted through the damping resistor, write current through the head is reduced. To achieve the desired value of write current through the head, more current must be generated to flow through both the head and the damping resistor. More importantly, the damping resistor slows the rise/fall times for write current transitions. This can adversely affect bit density. While resistive damping generally does reduce settling time, the slower rise/fall times may not be acceptable for high performance write circuits.
Accordingly, there is a need for a write driver having a simple control circuit that speeds up the turn-on and turn-off times of the drive transistors without diminishing head swing and that reduces write current overshoot through the head and settling time without adversely affecting the rise/fall time of the write current.